The present invention relates to a semiconductor device and a method of manufacturing the same, and more specifically relates to a semiconductor device including a MIM capacitor and a method of manufacturing the same.
The MIM (Metal Insulation Metal) capacitor is a capacitive element which can be formed in a semiconductor device having a multilayer interconnection structure. The capacitive element usually used in a semiconductor device includes a gate capacitor and the MIM capacitor. In the MIM capacitor, as compared with the gate capacitor, there is less need to increase the occupied area in the plane view of a semiconductor device itself in increasing the electric capacity of the capacitor. Moreover, the MIM capacitor has a small parasitic component as compared with the gate capacitor and is thus excellent in high frequency characteristics.
For this reason, there are increasingly more cases where the MIM capacitor is used in semiconductor devices. In order to suppress an initial failure of the MIM capacitor, it is very important to secure the flatness of a lower electrode constituting the MIM capacitor.
With an increase in the capacity of the MIM capacitor in recent years, it is predicted that the film thickness of a dielectric layer is thinned and that the area of the respective lower electrode and upper electrode in the plane view increases. As a result, the variation in the breakdown voltage of the MIM capacitor may increase and the failure (initial failure) due to this variation may increase.
The MIM capacitor is a capacitive element comprising a dielectric layer sandwiched by a lower electrode and an upper electrode. Usually, an insulative metal nitride film, nitride film, oxide film, or oxynitride film is used for the dielectric layer. Usually, the lower electrode comprises a copper-doped aluminum alloy whose lower portion and upper portion are sandwiched by at least one barrier layer comprising titanium nitride (TiN) or titanium metal (Ti).
In order to suppress the variation in the breakdown voltage of the MIM capacitor and improve the reliability of the MIM capacitor, the following two methods are considered to be used. One is a method of improving the reliability of the dielectric layer itself. The other one is a method of optimizing, for example, further flattening, the lower electrode corresponding to a stacked film layer in which the dielectric layer is to be stacked.
The above-described method of optimizing the lower electrode is disclosed, for example, in the following patent documents: Japanese Patent Laid-Open No. 2002-203915 (Patent Document 1); Japanese Patent Laid-Open No. 11-111947 (Patent Document 2); Japanese Patent Translation Publication No. 2007-515775 (Patent Document 3); Japanese Patent Laid-Open No. 2008-16464 (Patent Document 4); Japanese Patent Laid-Open No. 2008-270407 (Patent Document 5); Japanese Patent Laid-Open No. 2007-305654 (Patent Document 6); Japanese Patent Laid-Open No. 2007-188935 (Patent Document 7); and Japanese Patent Laid-Open No. 2001-210787 (Patent Document 8).